This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-078420, filed Mar. 21, 2000, the entire contents of which are incorporated herein by reference.
This invention relates to a semiconductor memory device and a method of testing such a device. More particularly, the present invention relates to a fuse data changing circuit for changing the data programmed in a fuse element and also to a built-in self-testing circuit. Such circuits can suitably be used for a dynamic semiconductor memory (DRAM).
In recent years, the technology of mounting a built-in self-testing circuit (BIST circuit) on a semiconductor memory and testing the semiconductor memory device comprising the memory by means of the BIST circuit instead of relying on an external memory tester has been given attention. Such a technology is desired particularly when testing a memory embedded logic that is referred to as system LSI in which a plurality of functional logics including a memory (memory macro) are integrated on a semiconductor chip to form a particular system configured in the single semiconductor chip.
Meanwhile, semiconductor memories manufactured recently with a high packing density typically comprise a redundant circuit so that any faulty memory cells may be replaced by redundant cells to relieve the memory and improve the yield of manufacturing semiconductor memories. The use of BIST circuits for obtaining cell replacement information (redundancy information) has been discussed (JSSCC, vol. 33, No. 11, November, 1998, pp 1731-1740).
However, it is necessary to increase the number of redundant memory cells in order to raise the relief efficiency. Then, the amount of redundancy information rises to consequently increase the pattern area of the registers for storing redundancy information and that of the BIST circuit in a semiconductor memory.
Moreover, as the number of redundant cells is increased in an attempt for improving the relief efficiency, there arises the need of a complicated replacement determining algorithm and a complex pattern sequence necessary for acquiring redundancy information to make the logic circuit for executing them highly complicated. As the result, unfortunately, a faulty rate of the BIST circuit is raised.
As pointed out above, the application of a BIST circuit to a known semiconductor memory entails the disadvantage that, as the number of redundancy memory cells is raised to improve the relief efficiency, the pattern area of the registers for storing redundancy information increases and there arises the need of a complicated replacement determining algorithm and a complex pattern sequence to make the logic circuit for executing them highly complicated and consequently raise the faulty rate of the BIST.
In view of the above identified circumstances it is therefore an object of the present invention to provide a semiconductor memory device comprising a BIST circuit for acquiring redundancy information that can be realized with a minimal increase of the pattern area and uses a simple algorithm to consequently reduce the faulty rate of the BIST circuit as well as a method of testing such a semiconductor memory device.
Another object of the present invention is to provide a semiconductor memory device in which data can be transferred to a following-stage circuit whenever necessary regardless of the data stored electrically in a memory element that is not data-rewritable so that the input to the following-stage circuit can be easily handled.
According to a first aspect of the present invention, there is provided a semiconductor memory device comprising a memory circuit having an array of regular memory cells and an array of redundancy memory cells; a storage element for storing redundancy data formed by non-volatile elements adapted to store externally programmable data but not adapted to electrically rewrite the stored data; a register for holding the redundancy data of the storage element when the semiconductor memory device is activated; a redundancy determining circuit for comparing the data held in the register and an externally input address to determine the use or non-use of any of the redundancy memory cells; and a redundancy data rewriting circuit for rewriting the redundancy data held in the register to a different redundancy data.
In the semiconductor memory device according to the first aspect of the present invention, the redundancy data rewriting circuit may be controlled by a signal from a test circuit mounted on a semiconductor chip of the semiconductor memory device or a signal of a test circuit provided outside the semiconductor chip. In the semiconductor memory device, the test circuit may be a built-in type test circuit for self-generating a test pattern. In the semiconductor memory device, the memory circuit may have an X, Y two-dimensional address space and two-dimensional redundancy memory cells, and the built-in test circuit may perform the sequence including the steps of changing the X addresses on the basis of a unit of redundancy, while fixing the Y address, and testing the X addresses of the unit of redundancy, while fixing the Y address to determine whether faulty memory cells are detected or not; using the Y redundancy memory cells when the faulty memory cells are not relieved by using the X redundancy cells alone, while using the X redundancy memory cells when the faulty memory cells are relieved by using the X redundancy cells alone; testing again the X addresses; continuing the test and the relief operation until no faulty memory cells are detected; performing the test and the relief operation to next and succeeding X addresses of the unit of redundancy after the elimination of faulty memory cells; shifting the Y address and performing a similar test in the X direction; and outputting a pass signal at the time of completion of the test of the last address of the unit of redundancy, while outputting a fail signal to end the test operation in the case of consuming all the redundancy cells before outputting a pass signal. In the semiconductor memory device, the built-in type test circuit may comprise a data generation circuit for generating a pattern of data to be written to the memory circuit; an address generation circuit for generating an address pattern to specify an address of the memory circuit; an expected value generation circuit for generating an expected value data relative to an output data of the memory circuit; a data comparison circuit for comparing the output data and the expected value data; and a redundancy allocation circuit for determining an allocation of the redundancy memory cells in response to an output of the data generation circuit and an output of the address generation circuit, the redundancy data rewriting circuit being controlled by an output of the redundancy allocation circuit. In the semiconductor memory device, the built-in test circuit may perform the sequence in which changing the addresses on the basis of a unit of redundancy, testing the addresses of the unit of redundancy to determine whether faulty memory cells are detected or not, and relieving the faulty memory cells by using the redundancy memory cells; inputting redundant information to the register by means of the redundancy data rewriting circuit; testing again the addresses; continuing the test and the relief operation until no faulty memory cells are detected; performing the test and the relief operation to next and succeeding addresses of the unit of redundancy after the elimination of faulty memory cells; outputting a pass signal at the time of completion of the test to the last addresses of the unit of redundancy, while outputting a fail signal to end the test operation in the case of consuming all the redundancy cells before outputting a pass signal.
In the semiconductor memory device according to the first aspect of the present invention, the semiconductor memory device may further comprise redundancy data read circuit for reading the data held in the register to the outside. In the semiconductor memory device, the redundancy data rewriting circuit may be controlled by a signal from a test circuit mounted on a semiconductor chip of the semiconductor memory device or a signal of a test circuit provided outside the semiconductor chip. In -the semiconductor memory device, the test circuit may be a built-in type test circuit for self-generating a test pattern. In the semiconductor memory device, the built-in type test circuit may comprise a data generation circuit for generating a pattern of data to be written to the memory circuit; an address generation circuit for generating an address pattern to specify an address of the memory circuit; an expected value generation circuit for generating an expected value data relative to an output data of the memory circuit; a data comparison circuit for comparing the output data and the expected value data; and a redundancy allocation circuit for determining an allocation of the redundancy memory cells in response to an output of the data generation circuit and an output of the address generation circuit, the redundancy data rewriting circuit being controlled by an output of the redundancy allocation circuit. In the semiconductor memory device, the built-in test circuit may perform the sequence in which changing the addresses on the basis of a unit of redundancy, testing the addresses of the unit of redundancy to determine whether faulty memory cells are detected or not, and relieving the faulty memory cells by using the redundancy memory cells; inputting redundant information to the register by means of the redundancy data rewriting circuit; testing again the addresses; continuing the test and the relief operation until no faulty memory cells are detected; performing the test and the relief operation to next and succeeding addresses of the unit of redundancy after the elimination of faulty memory cells; outputting a pass signal at the time of completion of the test to the last addresses of the unit of redundancy, while outputting a fail signal to end the test operation in the case of consuming all the redundancy cells before outputting a pass signal. In the semiconductor memory device, the memory circuit may have an X, Y two-dimensional address space and two-dimensional redundancy memory cells, and the built-in test circuit may perform the sequence including the steps of changing the X addresses on the basis of a unit of redundancy, while fixing the Y address, and testing the X addresses of the unit of redundancy, while fixing the Y address to determine whether faulty memory cells are detected or not; using the Y redundancy memory cells when the faulty memory cells are not relieved by using the X redundancy cells alone, while using the X redundancy memory cells when the faulty memory cells are relieved by using the X redundancy cells alone; testing again the X addresses; continuing the test and the relief operation until no faulty memory cells are detected; performing the test and the relief operation to next and succeeding X addresses of the unit of redundancy after the elimination of faulty memory cells; shifting the Y address and performing a similar test in the X direction; and outputting a pass signal at the time of completion of the test of the last address of the unit of redundancy, while outputting a fail signal to end the test operation in the case of consuming all the redundancy cells before outputting a pass signal.
According to a second aspect of the present invention, there is provided a semiconductor memory device comprising a storage element adapted to program data and not adapted to electrically rewrite the stored data; a transfer circuit for transferring the data stored in the storage element to a following-stage circuit; a changing circuit in the transfer circuit and adapted to selectively change the data to be transferred.
In the semiconductor memory device according to the second aspect of the present invention, the transfer circuit may further comprise a data holding circuit for holding the data stored in the storage element; and the changing circuit may be adapted to destroy the data held in the data holding circuit and change to a different data.
In the semiconductor memory device according to the second aspect of the present invention, the changing circuit may be adapted to inactivate the transfer of the data stored in the storage element and change to a different data.
According to a third aspect of the present invention, there is provided a method of testing a semiconductor memory device comprising an array of regular memory cells and an array of redundancy memory cells to be used for relief by means of a built-in type test circuit, the method comprising a step of performing a sequence of changing the addresses on the basis of a unit of redundancy, testing the addresses of the unit of redundancy to determine whether faulty memory cells are detected or not, and relieving the faulty memory cells by using the redundancy memory cells; inputting redundant information to the register; testing again the addresses; continuing the test and the relief operation until no faulty memory cells are detected; and performing the test and the relief operation to next and succeeding addresses of the unit of redundancy after the elimination of faulty memory cells; and a step of outputting a pass signal at the time of completion of the test to the last addresses of the unit of redundancy, while outputting a fail signal to end the test operation in the case of consuming all the redundancy cells before outputting a pass signal.
According to a fourth aspect of the present invention, there is provided a method of testing a semiconductor memory device comprising an X, Y two-dimensional address space and two-dimensional redundancy memory cells by means of a built-in type test circuit, the method performs the sequence including the steps of changing the X addresses on the basis of a unit of redundancy, while fixing the Y address, and testing the X addresses of the unit of redundancy, while fixing the Y address to determine whether faulty memory cells are detected or not; using the Y redundancy memory cells when the faulty memory cells are not relieved by using the X redundancy cells alone, while using the X redundancy memory cells when the faulty memory cells are relieved by using the X redundancy cells alone; testing again the X addresses; continuing the test and the relief operation until no faulty memory cells are detected; performing the test and the relief operation to next and succeeding X addresses of the unit of redundancy after the elimination of faulty memory cells; shifting the Y address and performing a similar test in the X direction; and outputting a pass signal at the time of completion of the test of the last address of the unit of redundancy, while outputting a fail signal to end the test operation in the case of consuming all the redundancy cells before outputting a pass signal.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.